- Involved in building verification environment for PCIe 1.0a PCISIG compliant core.
- Wrote PERL scripts for direct and regression testing.
- Involved in modeling behavioral entities in VHDL required for verification environment.
- Generated test cases for verifying the PCIe core.
- Developed the automated self checking feature in the Verification Environment.
- Developed Data Link Layer (DLL) Analyzer in VHDL required for verifying the Data Link Layer’s compatibility with PCISIG PCIe 1.0A compliance rules.
- Extending existing verification environments to improve the quality of testing
- Develop UVM Sequences at Top
- Develop/Modify Perl/Python scripts
- Debug, report, and work closely with design engineers
- Create testcase to ensure maximum coverage
- Analysis of the specification documents and Listing Down Features
- Developing Test Plans
- Coding Testbench Components
- Functional Coverage and Code Coverage
sr. verification engineer
- Involved in top level RTL verification.
- Generated C test cases for verifying the ARM based RTL core.
- Carried out Gate Level simulations for SDF back annotation.
- Actively participated in debugging the failures in Top level Specman/C test cases.
- Created and maintained register database for generating macros used in verification.
- Learnt Linux and sysytemverilog to construct protocol based on memory interface.
- Developing logic and code as per the client’s requirement.
- Developed a memory interface(AHB 3 Lite Protocol) to transfer heavy data by using systemverilog and cross checked the working by making test cases.
- software design and development using e language